PRIGROUP can get a bit confusing since the unimplemented bits are towards the LSb i.e. Note that LPC134x MCUs implement only 3 bits of Priority hence can give 8 unique priority levels. Similarly we can get the Priority Grouping table for LPC13xx devices like LPC1343/LPC1347 using the master table. which implement only 4 bits of interrupt priority is given below. Priority Grouping for other Cortex-M3 MCUs from the STM32 family like STM32F103, etc. STM32 (STM32F10xxx) Interrupt Priority Grouping This is shown below: LPC176x Interrupt Priority Grouping Priority Grouping NumberĪn Example with Priority Grouping of 5 on LPC17xx Devices which implement 5 bits for Priority is as follows: The remaining(lower) 3 bits are treated as Zeros. For example LPC17xx devices (like LPC1768/LPC1769) implement only 5 bits for Priority. The Priority Grouping Number value shown in the table is assigned to the PRIGROUP field of AIRCR.įor MCUs which implement less than 8 bits, the non-implemented bits are treated as Zeros in the table above. Any of the 8 possible grouping can be selected using the PRIGROUP field (bits) of the AIRCR (Application Interrupt and Reset Control Register). This Priority Grouping is common for all ARM Cortex-M3 processor based microcontrollers. Note: The split point or the Binary point denotes the segregation of Interrupt Priority Field (in IPR) into Group-Priority bits denoted by ‘ x‘ and Sub-Priority bits denoted by ‘ y‘. The master table which assigns a Priority Grouping Number for each of the 8 possible divisions is shown below: Priority Grouping Number Interrupt Priority Groups in ARM Cortex-M3īased on the sub-divisions, priority groups are formed depending on how many bits are used for preemption and sub-priority levels. It also doesn’t implement Interrupt Priority Grouping. This implementation is fixed for all MCUs which use Cortex-M0 (ARMv6-M) CPU. Also note that, if pending ISRs have same Group and Sub-Group priority then the Interrupt having the lowest IRQ number will be executed first.Ĭortex-M0 Processor only implements 2 bits in the priority field and rest bits are always treated as Zeros, thereby supporting only 4 unique priority levels. In this case the sub-priority will determine which Interrupt gets executed first. Sub-Priority Level: This comes into picture when there are multiple pending interrupts having same preemption or Group Priority.Lower priority values denote higher priority & vice-versa. An Interrupt will preempt the execution of the current Interrupt, if its Group Priority is higher than the Interrupt being currently serviced. This is the main priority level which defines the preemption of interrupt exceptions or IRQs. Preemption Priority or Group Priority level: This is upper part(sub-field) of the 8-bit priority field.In Cortex-M3, each of these fields can be further sub-divided into two parts, which are: The byte offset is the remainder of “ m/4” i.e.The IPR number n for Interrupt m is the Quotient of “ m/4” i.e.PRI_m is the Priority field for Interrupt m ( IRQm). Here, IRPn represents nth Interrupt Priority Register. Each priority register is 32-bits wide and holds 4 priority fields. These priority fields are stored in the Interrupt Priority Register. Generally the implemented bits are in proportion with number of external(peripheral) interrupts a given microcontroller supports. But, not all of the ARM Microcontrollers implement 8 bits for priority levels, in which case the remaining priority bits are treated as Zeros because the field size is fixed to 8 bits.

NVIC in ARM Cortex-M3 (ARMv7-M) implements fixed 8-bit priority fields in Interrupt Priority Register ( IPR), thereby giving us up to 256(2 8) priority levels. Microcontrollers based on ARM Cortex-M processor feature Nested Vectored Interrupt Controller or NVIC for handling interrupts.

Stm32 part number decoding